Logical operation circuit and logical operation method

ABSTRACT

To provide a logical operation circuit and a logical operation method which can perform a logical operation using a ferroelectric capacitor. A logical operation circuit  1  has ferroelectric capacitors CF 1  and CF 2  and a transistor MP. The ferroelectric capacitor CF 1  can retain a polarization state P 1  corresponding to a logical operator. In an operation and storage process, a source potential Vdd corresponding to first operation target data y 1 =1 and a ground potential GND corresponding to second operation target data y 2 =0 are given to a first terminal  3  and a second terminal  5 , respectively, of the ferroelectric capacitor CF 1.  The polarization state of the ferroelectric capacitor CF 1  is thereby shifted to P 4 . A residual polarization state corresponding to the polarization state P 4  is P 2 . The residual polarization state changes (P 1 , P 1 , P 2  or P 1 ) depending on the combination of y 1  and y 2  (0-0, 0-1, 1-0 and 1-1). In a reading process after that, an output corresponding to the residual polarization state is obtained via the transistor MP.

CROSS-REFERENCE TO RELATED APPLICATIONS

The entire disclosure of a Japanese patent application No. 2002-18662filed on Jan. 28, 2002 including its specification, claims, drawings,and summary is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present invention relates to a logical operation circuit and alogical operation method and, more particularly, to a logical operationcircuit, a logical operation device and a logical operation method usinga non-volatile memory element, such as a ferroelectric capacitor.

BACKGROUND ART

A non-volatile memory is known as a circuit using a ferroelectriccapacitor. It is possible to realize a rewritable non-volatile memorywhich can operate on a low voltage by using a ferroelectric capacitor.

However, such a conventional circuit cannot perform a logical operationon data even if it can store data.

DISCLOSURE OF THE INVENTION

An object of this invention is to solve the problem of such aconventional circuit using a ferroelectric capacitor and to provide alogical operation circuit, a logical operation device and a logicaloperation method which can perform a logical operation on data using anon-volatile memory element, such as a ferroelectric capacitor.

A logical operation circuit according to this invention comprises: afirst ferroelectric capacitor, first and second signal lines and anoperation result output section. The first ferroelectric capacitor canretain a polarization state corresponding to a specified logicaloperator, and has first and second terminals. The first and secondsignal lines can provide first and second operation target data to thefirst and second terminals, respectively, of the ferroelectric capacitorretaining the polarization state corresponding to the logical operator,and are connected to the first and second terminals, respectively. Theoperation result output section can output the result of a logicaloperation performed on the first and second operation target dataaccording to the logical operator based on a polarization state of theferroelectric capacitor generated by providing the two operation targetdata to the ferroelectric capacitor, and is connected to the firstsignal line.

A logical operation circuit according to this invention comprises: afirst ferroelectric capacitor having first and second terminals; firstand second signal lines connected to the first and second terminals,respectively; a second ferroelectric capacitor having a third terminalconnected to the first signal line and a fourth terminal connected to afirst reference potential; and an output transistor. The outputtransistor has a control terminal connected to the first signal line andan output terminal for outputting an output signal corresponding to acontrol signal inputted into the control terminal, and becomes off whena potential on the first reference potential side from its thresholdvoltage is given as the control signal and becomes on when a potentialon a second reference potential side from its threshold voltage is givenas the control signal. In the logical operation circuit, the followingoperation is performed: The first and second signal lines are connectedto one of the first and second reference potentials and the other of thefirst and second reference potentials, respectively, to generate apolarization state corresponding to a specified logical operator in thefirst ferroelectric capacitor. Then, first and second operation targetdata are provided to the first and second signal lines, respectively, toshift the polarization state of the first ferroelectric capacitor to onecorresponding to the combination of the logical operator and the firstand second operation target data. The first and second signal lines areboth connected to the first reference potential to precharge the firstsignal line to the first reference potential without changing theresidual polarization state of the first ferroelectric capacitor. Afterthat, the application of voltage to the first signal line is stopped andthe second signal line is connected to the second reference potential.Then, an output signal which is generated at the output terminal of theoutput transistor in response to a potential generated in the firstsignal line when the second signal line is connected to the secondreference potential can be obtained as the result of a logical operationperformed on the first and second operation target data according to thelogical operator.

A logical operation circuit according to this invention comprises: anon-volatile memory element which can retain a non-volatile statecorresponding to a specified logical operator and which has first andsecond terminals; and an operation result output section which, based ona state of the non-volatile memory element generated by providing firstand second operation target binary data y1 and y2 to the first andsecond terminals, respectively, of the non-volatile memory element,outputs the result of a logical operation performed on the first andsecond operation target data y1 and y2 according to the logical operatoras operation result binary data “z”. When the non-volatile statecorresponding to the specified logical operator is represented by statebinary data “s”, the operation result data “z” substantially satisfiesthe following relation:

-   -   z=/s AND y1 NAND /y2 OR s AND (y1 NOR /y2).

A logical operation circuit according to this invention comprises: anon-volatile memory element for retaining a non-volatile statecorresponding to a specified logical operator; and an operation resultoutput section which, based on a state of the non-volatile memoryelement generated by providing first and second operation target data tothe non-volatile memory element, outputs the result of a logicaloperation performed on the first and second operation target dataaccording to the logical operator, and which is connected to a firstterminal of the non-volatile memory element.

A logical operation method according to this invention comprises thesteps of: causing a ferroelectric capacitor having first and secondterminals to retain a polarization state corresponding to a specifiedlogical operator; providing first and second operation target data tothe first and second terminals, respectively, of the ferroelectriccapacitor retaining the polarization state corresponding to the logicaloperator; and obtaining the result of a logical operation performed onthe first and second operation target data according to the logicaloperator based on the polarization state of the ferroelectric capacitorgenerated by providing the two operation target data to theferroelectric capacitor.

Although the features of this invention can be expressed as above in abroad sense, the constitution and content of this invention, as well asthe object and features thereof, will be apparent with reference to thefollowing disclosure, taken in connection with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating a logical operation circuit 1according to an embodiment of this invention;

FIG. 2 is a timing diagram illustrating the operation of the logicaloperation circuit 1;

FIG. 3A is a view illustrating the state of the logical operationcircuit 1 during a reset process;

FIG. 3B is a graph illustrating the polarization state of aferroelectric capacitor CF1 during the reset process;

FIG. 4A is a view illustrating the state of the logical operationcircuit 1 during an operation and storage process;

FIG. 4B is a graph illustrating the polarization state of theferroelectric capacitor CF1 during the operation and storage process;

FIG. 5A is a view illustrating the state of the logical operationcircuit 1 during a retention process;

FIG. 5B is a graph illustrating the polarization state of theferroelectric capacitor CF1 during the retention process.

FIG. 6A is a view illustrating the state of the logical operationcircuit 1 during a reading process;

FIG. 6B is a graph illustrating the polarization state of theferroelectric capacitor CF1 during the reading process;

FIG. 7A is a table showing the relation among first and second operationtarget data y1 and y2 and the value of an output line ML when thelogical operation circuit 1 is caused to perform a logical operation“ML=y1 NAND /y2”;

FIG. 7B is a table showing the relation among first and second operationtarget data y1 and y2 and the value of the output line ML when thelogical operation circuit 1 is caused to perform a logical operation“ML=y1 NOR /y2”;

FIG. 8A is a block diagram illustrating the logical operation circuit 1;

FIG. 8B is a block diagram illustrating a serial adder 21 using thelogical operation circuit 1;

FIG. 9 is a circuit diagram of the serial adder 21 shown in FIG. 8Brealized using the logical operation circuits 1;

FIG. 10 is a timing diagram illustrating control signals which are givento logical operation circuits constituting a first block BK1 and logicaloperation circuits constituting a second block BK2;

FIG. 11 is block diagram illustrating an example of the constitution ofa series-parallel pipeline multiplier using the logical operationcircuits 1 shown in FIG. 1;

FIG. 12 is a view used to explain the operation of a pipeline multiplier141;

FIG. 13 is a block diagram illustrating the constitution of the secondlevel operation section 141 b of the pipeline multiplier 141;

FIG. 14 is a logical circuit diagram illustrating the constitution ofthe second level operation section 141 b;

FIG. 15A is a plan view schematically illustrating a part of a logicaloperation circuit using a TMR element 151 as a non-volatile memoryelement;

FIG. 15B and FIG. 15C are cross-sectional views taken along the linesb-b and c-c, respectively, in FIG. 15A;

FIG. 16A to FIG. 16D are views used to explain the relation between thedirections of currents IC1 and IC2 which are passed through the inputlines 167 and 169, respectively, in a writing process and the changes inthe magnetizing direction of the ferromagnetic layer 163; and

FIG. 17A and FIG. 17B are views used to explain a method for controllingthe transistor MP based on data written into the TMR element 151, thatis, a method for performing a reading process.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a circuit diagram illustrating a logical operation circuit 1according to an embodiment of this invention. The logical operationcircuit 1 has a first ferroelectric capacitor CF1, a secondferroelectric capacitor CF2 as a load element, a transistor MP as anoutput transistor, and transistors M1, M2, M3 and M4. The secondferroelectric capacitor CF2 and the transistor MP constitute anoperation result output section. The transistors MP, M1, M2, M3 and M4are N-channel MOSFETs (metal oxide semiconductor field effecttransistors).

The ferroelectric capacitor CF1 has a first terminal 3 connected to afirst signal line 7 and a second terminal 5 connected to a second signalline 9. The first signal line 7 is connected to a gate terminal as acontrol terminal of the transistor MP.

The ferroelectric capacitor CF2 has a third terminal 11 connected to thefirst signal line 7 and a fourth terminal 13 connected to a groundpotential GND as a first reference potential.

The first signal line 7 is connected to a first bit line BY1 via thetransistor M1 and to the ground potential GND via the transistor M3. Thesecond signal line 9 is connected to a second bit line BY2 via thetransistor M2 and to a source potential Vdd as a second referencepotential via the transistor M4.

The transistors M1 and M2 have gate terminals connected to an inversionclock line /CLK. The transistors M3 and M4 have gate terminals connectedto a reset line RS and a clock line CLK, respectively. The negation(inversion signal) of a binary number (binary signal) “A” is hereinrepresented as “/A”, unless otherwise stated.

The transistor MP has an input terminal connected to the groundpotential GND via a transistor M5 and an output terminal connected to anoutput line ML. The output line ML is connected to the source potentialVdd via a transistor M6. The transistors M5 and M6 have gate terminalsconnected to a preset line PRE. The transistor M5 is an N-channelMOSFET, and the transistor M6 is a P-channel MOSFET.

Description will be made of the operation of the logical operationcircuit 1 shown in FIG. 1. FIG. 2 is a timing diagram illustrating theoperation of the logical operation circuit 1.

In a reset process, an “H” potential (namely, the source potential Vdd)is given to both the clock line CLK and the reset line RS. An “L”potential (namely, the ground potential GND) is given to both the bitlines BY1 and BY2.

FIG. 3A is a view illustrating the state of the logical operationcircuit 1 during the reset process, and FIG. 3B is a graph illustratingthe polarization state of the ferroelectric capacitor CF1 during thereset process. As shown in FIG. 3A, the transistors M1 and M2 are bothoff and the transistors M3 and M4 are both on. Thus, “L” and “H” areapplied to the first terminal 3 and the second terminal 5, respectively,of the ferroelectric capacitor CF1.

At this time, the polarization state of the ferroelectric capacitor CF1is shifted from P1 or P2 to P3 as shown in FIG. 3B. When the applicationof voltages to the first terminal 3 and the second terminal 5 isstopped, the polarization state of the ferroelectric capacitor CF1 isshifted from P3 to a residual polarization state P1. The residualpolarization state P1 corresponds to a logical operator NAND (negativeAND) as described later. As described above, a logical operator of thelogical operation circuit 1 can be set by a reset process.

Although one of input/output terminals of the transistor M3 is connectedto the ground potential GND and one of input/output terminals of thetransistor M4 is connected to the source potential Vdd in FIG. 3A, thisinvention is not limited thereto.

For example, in contrast to the case shown in FIG. 3A, one of theinput/output terminals of the transistor M3 may be connected to thesource potential Vdd and one of the input/output terminals of thetransistor M4 may be connected to the ground potential GND. In thiscase, the polarization state of the ferroelectric capacitor CF1 isshifted to P4 by the reset process in contrast to the case shown in FIG.3A. Then, when application of voltages to the first terminal 3 and thesecond terminal 5 is stopped, the polarization state of theferroelectric capacitor CF1 is shifted from P4 to a residualpolarization state P2. The residual polarization state P2 corresponds toa logical operator NOR (negative OR) as described later.

Either of the ground potential GND or the source potential Vdd may beapplied to one of the input terminals of the transistor M3 and the othermay be applied to one of the input/output terminals of the transistorM4. A desired logical operator can be thereby selected by the resetprocess.

The residual polarization states P1 and P2 may be referred to as “firstresidual polarization state” (s=0) and “second residual polarizationstate” (s=1), respectively.

In this process, since an “L” is given to the preset line PRE as shownin FIG. 3A, the transistors M5 and M6 are off and on, respectively.Thus, the output line ML has an “H”.

As shown in FIG. 2, the reset process is followed by an operation andstorage process (O/W). In an operation and storage process, an “L”potential is given to both the clock line CLK and the reset line RS.First and second operation target data y1 and y2 are given to the bitlines BY1 and BY2, respectively.

In this embodiment, an “H” is given to the bit line BY1 when y1=1 and an“L” is given to the bit line BY1 when y1=0. The relation between y2 andthe bit line BY2 is the same as that between y1 and the bit line BY1.Thus, in the operation and storage process shown in FIG. 2, y1=1 andy2=0 are given as the first and second operation target data,respectively.

FIG. 4A is a view illustrating the state of the logical operationcircuit 1 during the operation and storage process, and FIG. 4B is agraph illustrating the polarization state of the ferroelectric capacitorCF1 during the operation and storage process. As shown in FIG. 4A, thetransistors M1 and M2 are both on and the transistors M3 and M4 are bothoff. Thus, “H” and “L” are applied to the first terminal 3 and thesecond terminal 5, respectively, of the ferroelectric capacitor CF1.

At this time, the polarization state of the ferroelectric capacitor CF1is shifted from P1 to P4 as shown in FIG. 4B. When y1=0 and y2=1 aregiven as the first and second operation target data, respectively, thepolarization state of the ferroelectric capacitor CF1 is shifted from P1to P3. When y1=0 and y2=0 are given or when y1=1 and y2=1 are given, thepolarization state of the ferroelectric capacitor CF1 is maintained atP1.

In the operation and storage process, a logical operation is performedon the first and second operation target data y1 and y2 according to thelogical operator set by the reset process and a polarization statecorresponding to the result of the logical operation is generated in theferroelectric capacitor CF1.

Also in this process, since an “L” is given to the preset line PRE asshown in FIG. 4A, the transistors M5 and M6 are off and on,respectively. Thus, the output line ML has an “H”.

As shown in FIG. 2, the operation and storage process is followed by aretention process (Ret.). In a retention process, “L” and “H” are givento the clock line CLK and the reset line RS, respectively, and an “L” isgiven to both the bit lines BY1 and BY2.

FIG. 5A is a view illustrating the state of the logical operationcircuit 1 during the retention process, and FIG. 5B is a graphillustrating the polarization state of the ferroelectric capacitor CF1during the retention process. As shown in FIG. 5A, the transistors M1,M2 and M3 are all on and the transistor M4 is off. Thus, an “L” isapplied to both the first terminal 3 and the second terminal 5 of theferroelectric capacitor CF1.

At this time, the polarization state of the ferroelectric capacitor CF1is shifted from P4 to P2 as shown in FIG. 5B. When the polarizationstate of the ferroelectric capacitor CF1 has become P3 by the operationand storage process, it is shifted from P3 to P1. When the polarizationstate of the ferroelectric capacitor CF1 has become P1 by the operationand storage process, it is maintained as it is.

Also in this process, since an “L” is given to the preset line PRE asshown in FIG. 5A, the transistors M5 and M6 are off and on,respectively. Thus, the output line ML has an “H”.

As shown in FIG. 2, the retention process is followed by a readingprocess (Read). In a reading process, “H” and “L” are given to the clockline CLK and the reset line RS, respectively, and an “L” is given toboth the bit lines BY1 and BY2.

FIG. 6A is a view illustrating the state of the logical operationcircuit 1 during the reading process, and FIG. 6B is a graphillustrating the polarization state of the ferroelectric capacitor CF1during the reading process. As shown in FIG. 6A, the transistors M1, M2and M3 are all off and the transistor M4 is on. Thus, an “H” is appliedto the second terminal 5 of the ferroelectric capacitor CF1.

According to a graphical analysis, when the polarization state of theferroelectric capacitor CF1 has become P2 by the above retentionprocess, that is, when y1=1 and y2=0 have been given as the first andsecond operation target data, respectively, the polarization state ofthe ferroelectric capacitor CF 1 is shifted from P2 to P6 by the readingprocess as shown in FIG. 6B.

At this time, the polarization state of the ferroelectric capacitor CF2is shifted from P12 to P6. That is, the potential Va at the gateterminal of the transistor MP is shifted from the potential of P12(ground potential GND) to the potential of P6.

When the polarization state of the ferroelectric capacitor CF1 hasbecome P1 by the above retention process, that is, when Y1=0 and y2=0have been given as the first and second operation target data,respectively, when y1=1 and y2=1 have been given as the first and secondoperation target data, respectively, or when y1=0 and y2=1 have beengiven as the first and second operation target data, respectively, thepolarization state of the ferroelectric capacitor CF1 is shifted from P1to P5. At this time, the polarization state of the ferroelectriccapacitor CF2 is shifted from P13 to P5. That is, the potential Va atthe gate terminal of the transistor MP is shifted from the potential ofP13 (ground potential GND) to the potential of P5.

The difference between the threshold voltage Vth of the transistor MPand the ground potential GND is set to have an absolute value Vath(which is equal to Vth in this embodiment) which is smaller than thepotential difference between P12 and P6 and greater than the potentialdifference between P13 and P5.

Thus, when the polarization state of the ferroelectric capacitor CF1 hasbecome P2 by the retention process (that is, when s=1), the transistorMP becomes on, and when the polarization state of the ferroelectriccapacitor CF1 has become P1 by the retention process (that is, whens=0), the transistor MP becomes off.

Since an “H” is given to the preset line PRE in the reading process asshown in FIG. 6A, the transistor M5 and M6 are on and off, respectively.Thus, the value of the output line ML differs depending on whether thetransistor MP is on or off.

That is to say, the value of the output line ML becomes “L” or “H”depending on whether the transistor MP is on or off (see FIG. 6A). Whenthe values “L” and “H” of the output line ML are associated with logics“0” and “1”, respectively, the relation among the first and secondoperation target data y1 and y2 and the value of the output line ML (theresult of the logical operation) is as shown in FIG. 7A.

As can be understood from FIG. 7A, the logical operation circuit 1performs a logical operation “ML=y1 NAND /y2 (negative AND of y1 and/y2)”.

As shown in FIG. 2, by repeating a cycle configured with the resetprocess to the reading process, a logical operation can be performed onfirst and second operation target data of various types.

In this embodiment, the logical operator is set to NAND (negative AND)by setting the polarization state of the ferroelectric capacitor CF1 tobe P1 (that is, S=0) by the reset process. However, the logical operatorcan be set to NOR (negative OR) by setting the polarization state of theferroelectric capacitor CF1 to be P2 (that is, S=1) by the resetprocess.

FIG. 7B is a table showing the relation among the first and secondoperation target data y1 and y2 and the value of the output line ML (theresult of the logical operation) when the logical operator is set toNOR. It can be understood from FIG. 7B that the logical operationcircuit performs a logical operation “ML=y1 NOR /y2 (negative OR of y1and /y2)” in this case.

FIG. 8A is a block diagram of the logical operation circuit 1 shown inFIG. 1. In FIG. 8A, the ferroelectric capacitor CF1 is represented as amemory function block 15, and the ferroelectric capacitors CF1 and CF2and the transistor MP are represented as a logical operation functionblock 17.

That is, the logical operation circuit 1 shown in FIG. 1 can be regardedas a circuit having a memory function block 15 for storing a specifiedlogical operator, a logical operation function block 17 for performing alogical operation on first and second operation target data y1 and y2according to the logical operator, and a transistor MP which is turnedon or off according to the result of the logical operation.

FIG. 8B is a block diagram illustrating a serial adder 21 using thelogical operation circuit 1 shown in FIG. 1. The serial adder 21 has afull adder 23 and a register function section 25. The full adder 23receives two 1-bit binary numbers “a” and “b” and a carry “c” from alower bit and performs an addition to produce the sum and the carry ofthe binary numbers “a” and “b” and the carry “c” from a lower bit. Theregister function section 25 inputs the carry as a carry “c” at additionof the next digit under the control of the clock line CLK.

To add two multi-bit numbers A and B using the serial adder 21, theabove addition process is performed on the least significant bit to themost significant bit.

FIG. 9 is a circuit diagram of the serial adder 21 shown in FIG. 8B,which is realized using the logical operation circuits 1. As shown inFIG. 9, the serial adder 21 has a first block BK1 and a second blockBK2.

The first block BK1 has three logical operation circuits 31, 41 and 61each having the same constitution as the logical operation circuit 1shown in FIG. 1. The logical operation circuits 31, 41 and 61 have aclock line CLK, an inversion clock line /CLK and a reset line RS whichare similar to those of the logical operation circuit 1 shown in FIG. 1,and control signals which are similar to those in the logical operationcircuit 1 are given to the control signal lines. The logical operationcircuits 31, 41 and 61 have an inversion reset line /RS as a controlsignal line corresponding to the preset line PRE of the logicaloperation circuit 1. An inversion signal of the reset line RS is givento the inversion reset line /RS.

The second block BK2 has four logical operation circuits 32, 42, 52 and62, each having the same constitution as the logical operation circuit 1shown in FIG. 1. In the logical operation circuits 32, 42, 52 and 62,the control signal lines are connected in the same manner as those inthe logical operation circuits 31, 41 and 61 constituting the firstblock BK1 except that the connection of the clock line CLK and theinversion clock line /CLK is reversed from that in the first block BK1.

FIG. 10 is a timing diagram illustrating control signals which are givento the logical operation circuits 31, 41 and 61 constituting the firstblock BK1 and the logical operation circuits 32, 42, 52 and 62constituting the second block BK2. It can be understood that in thelogical operation circuits constituting the first block BK1 and thelogical operation circuits constituting the second block BK2, one set ofprocesses is performed during one period of the control signal given tothe clock line CLK, and the processes of those circuits are shifted fromeach other by a half period of the control signal.

As shown in FIG. 9, the logical operation circuit 31 of the first blockBK1 has a memory function block 33 in which a logical operator has beenstored as in the case with the logical operation circuit 1 (see FIG. 8A)and a logical operation function block 35 for performing an operation on“b” and a carry “c” from a lower bit as first and second operationtarget data according to the logical operator.

The on and off of a transistor 37 is controlled according to the resultof the operation. Thus, the transistor 37 outputs “b NAND /c”. When thelogical operators AND and OR are represented as “·” and “+”,respectively, the output from the transistor 37 is represented as“/(b·/c)”.

Similarly, the logical operation circuit 41 has a transistor 47 whichoutputs “/(c·/b)”.

A wired OR 51 calculates the negative logic OR (namely positive logicAND) of the output from the transistor 37 of the logical operationcircuit 31 and the output from the transistor 47 of the logicaloperation circuit 41. Thus, the value of the output line ML11 of thewired OR 51 becomes “/((b·/c)+(c·/b))”. An inverter 53 shown in FIG. 9therefore outputs “(b·/c)+(c·/b))”, namely “b EXOR c” (the exclusive ORof “b” and “c”).

The value of the output line ML12 connected to the output terminal of atransistor 67 of the logical operation circuit 61 becomes “/(b·c)”.Thus, an inverter 53 shown in FIG. 9 outputs (b·c).

Similarly, in the second block BK2, the sum, which is the output from aninverter 54, namely the output from the serial adder 21, is “a EXOR bEXOR c”. The output from an inverter 56, namely the carry from theserial adder 21 is “b·c+a·(b EXOR c)”.

As described above, the serial adder 21 can be constituted with ease byusing the logical operation circuits 1 shown in FIG. 1.

FIG. 11 is block diagram illustrating an example of the constitution ofa series-parallel pipeline multiplier using the logical operationcircuits 1 shown in FIG. 1. A pipeline multiplier 141 is configured todivide the multiplication of a 4-bit multiplicand “s” and a 4-bitmultiplier “b” into the same number of levels as the number of bits ofthe multiplier “b”, namely four levels, and performs the operation insequence. As shown in FIG. 11, first to fourth level operation sections141 a to 141 d perform first to fourth level operations, respectively.

For example, the second level operation section 141 b has an AND circuit142 as an element partial product generation section and a serialpipeline full adder 143 as an element operation device. In the drawing,each “st” with a square around it is a symbol representing a storagesection and each “+” with a circle around it is a symbol representing afull adder. The second and third level operation sections 141 c and 141d have the same constitution. The first level operation section 141 adoes not have a full adder.

FIG. 12 is a view used to explain the operation of the pipelinemultiplier 141. In the drawing, the operations of the first to fourthlevels are shown from left to light. In the operation of each level,steps (time) proceed from top to bottom. In the drawing, each “V” with acircle around it is a symbol representing the AND circuit 142. Also inthe drawing, each broken line with a downward-pointing arrow connectingadjacent symbols representing full adders within the same level in thesecond to fourth levels represents a flow of a carry.

For example, the operation of the second level operation section 141 bof the pipeline multiplier 141, namely the second level operation, isshown in the second column from the left in FIG. 12. Thus, the operationin the third step (third cycle) of the second level operation section141 b, for example, is shown in the third row from the top in the secondcolumn from the left, that is in the area “Q” in the drawing. Theoperation in the third step of the second level operation section 141 bof the pipeline multiplier 141 will be described.

First, the AND circuit 142 calculates the AND of an operation targetmultiplicand bit s1 as an object of the operation of the second level ofthe four bits constituting the multiplicand “s” and a bit b1corresponding to the second level of the four bits constituting themultiplier “b”. Then, the pipeline full adder 143 calculates the sum ofthree binary numbers: the AND calculated as above, the partial productproduced in the previous level, namely the first level, and the carry ofa bit s0, which is the bit before the operation target multiplicand bits1, in the second level.

The result of the calculation in the pipeline full adder 143 is sent asa partial product of the operation target multiplicand bit s1 in thesecond level to the third level as the next level. The carry generatedby the addition is stored as a carry of the operation targetmultiplicand bit s1 in the second level.

The third and fourth level operation sections 141 c and 141 d performoperations in the same manner. The first level operation section 141 acalculates an AND as an element partial product but does not perform anaddition.

FIG. 13 is a block diagram illustrating the constitution of the secondlevel operation section 141 b of the pipeline multiplier 141. FIG. 14 isa logical circuit diagram illustrating the constitution of the secondlevel operation section 141 b. Each of small and wide rectangles in FIG.14 represents a storage section. The second level operation section 141b is configured to divide the operation of the second level into fourstages and execute them in sequence.

As shown in FIG. 13, the second level operation section 141 b has firstto fourth stage operation sections 145 a to 145 d for performing theoperations of the first to fourth stages, respectively. In the drawing,each “FP” with a square around it represents the logical operationcircuit 1 (functional pass gate) shown in FIG. 1.

The first stage operation section 145 a fetches one bit as the currentoperation target of the bits constituting the multiplicand “s” andstores it as an operation target multiplicand bit sj.

The second stage operation section 145 b calculates and stores the ANDof the operation target multiplicand bit sj having been stored in theprevious stage and a bit b1 corresponding to the second level of thebits constituting the multiplier “b” as an element partial product ofthe operation target multiplicand bit sj in the second level using theAND circuit 142, and fetches and stores the operation targetmultiplicand bit sj having been stored in the first stage.

The third and fourth stage operation sections 145 c and 145 d calculatethe sum of three binary numbers: a partial product in the second levelcalculated in the previous stage, a partial product Pj in the firstlevel, and a carry C1 of the bit before the operation targetmultiplicand bit sj in the second level and stores it as a partialproduct Pj+1 of the operation target multiplicand bit sj in the secondlevel, and store a new carry generated by the addition as a carry of theoperation target multiplicand bit sj in the second level, using thepipeline full adder 143.

The third and fourth stage operation sections 145 c and 145 d also fetchthe operation target multiplicand bit sj having been stored in thesecond stage and stores it as an operation target multiplicand bit sj+1for the third level as the next level.

The third and fourth level operation sections 141 c and 141 d have thesame constitution as the second level operation section b. The firstlevel operation section 141 a, however, does not have a logicaloperation circuit for performing a full addition.

The pipeline full adder 143 shown in FIG. 13 may be considered as alogical operation device for performing operations of first and secondaddition stages corresponding to the third and fourth stages,respectively. In this case, the pipeline full adder 143 has first andsecond addition stage operation sections for performing the first andsecond addition stage operations, respectively.

The first and second addition stage operation sections constituting thepipeline full adder 143 are circuits obtained by removing, from thethird and fourth level operation sections 145 c and 145 d, the logicaloperation circuits 1 (functional pass gates) at the right-hand end ofFIG. 13.

That is, the first addition stage operation section calculates andstores a binary number corresponding to the exclusive OR of binarynumbers corresponding to an augend and an addend as a first additionresult using a pair of logical operation circuits 1 connected inparallel, and stores a carry outputted in the immediately previouslyperformed second addition stage.

The second addition stage operation section calculates and stores abinary number corresponding to the exclusive OR of the first additionresult calculated in the first addition stage and a binary numbercorresponding to the carry having been stored in the first additionstage as a second addition result and outputs the second additionsresult as the addition result of the pipeline full adder 143 usinganother pair of logical operation circuits 1 connected in parallel, andcalculates and stores the carry of the addition using a plurality oflogical operation circuits 1.

Although a ferroelectric capacitor is used as a load element in theabove embodiments, this invention is not limited thereto. For example, aparaelectric capacitor may be used as the load element. When aparaelectric capacitor is used as the load element, a capacitor intendedfor the purpose may be formed or the parasitic capacitance between thefirst reference potential and the first signal line may be used as theload element. The gate capacitance of the output transistor can be alsoused as the load element.

The load element is not limited to a capacitor. A resistor may be usedas the load element. When a resistor is used as the load element, bothends of the resistor serve as the third and fourth terminals,respectively.

A transistor may be used as the load element. When an FET (field effecttransistor), for example, is used as the load element, a pair ofinput/output terminals (a drain terminal and a source terminal) of theFET serve as the third and fourth terminals, respectively. In this case,it is preferable to apply a suitable bias voltage, such as the sourcepotential Vdd, to the gate terminal of the FET.

As the load element, a capacitor, a resistor and a transistor may beused in any combination.

Although the output transistor is an N-channel MOSFET in the aboveembodiments, this invention is not limited thereto. For example, thisinvention is applicable when the transistor MP is a P-channel MOSFET,for example. Also, this invention is applicable when the outputtransistor is a transistor other than a MOSFET or when the operationresult output section does not have an output transistor.

Although a ferroelectric capacitor is used as a non-volatile memoryelement in the above embodiments, the non-volatile memory element inthis invention is not limited to a ferroelectric capacitor. In general,an element having hysteresis characteristics can be used as anon-volatile memory element.

FIG. 15A to FIG. 17B are views used to explain an example of a logicaloperation circuit using a TMR (tunnel magnetoresistance) element (tunnelmagnetoresistive element) as a non-volatile memory element. FIG. 15A isa plan view schematically illustrating a part of a logical operationcircuit using a TMR element 151 as a non-volatile memory element. FIG.15B and FIG. 15C are cross-sectional views taken along the lines b-b andc-c, respectively, in FIG. 15A.

As shown in FIG. 15A to FIG. 15C, the TMR element 151 comprises a thinfilm like non-magnetic layer 165 of a dielectric material and a pair offerromagnetic layers 161 and 163 of a ferromagnetic material. Theferromagnetic layers 161 and 163 are laminated with the non-magneticlayer 165 interposed therebetween. The TMR element 151 is interposedbetween a pair of input lines 167 and 169. The input lines 167 and 169are arranged in contact with the ferromagnetic layers 161 and 163,respectively.

The input lines 167 and 169 correspond to the first and second signallines, respectively. The portions of the ferromagnetic layers 161 and163 in contact with the input lines 167 and 169 correspond to first andsecond terminals 161 a and 163 a, respectively, of the non-volatileelement.

A current can be passed in a desired direction through the input lines167 and 169. The ferromagnetic layer 163 is referred also to as a freelayer. The magnetizing direction of the ferromagnetic layer 163 ischanged depending on the combination of currents flowing through theinput lines 167 and 169. The ferromagnetic layer 161 is referred also toas a fixed layer. The magnetizing direction of the ferromagnetic layer161 is not changed by the currents flowing through the input lines 167and 169. In this example, the magnetizing direction of the ferromagneticlayer 161 is fixed in the rightward direction (first magnetizingdirection) in the drawing.

FIG. 16A to FIG. 16D are views used to explain the relation between thedirections of currents IC1 and IC2 which are passed through the inputlines 167 and 169, respectively, in a writing process and the changes inthe magnetizing direction of the ferromagnetic layer 163. In FIG. 16A toFIG. 16D, IC1=0 represents that the current IC1 is flowing in adirection perpendicular to the plane of the drawing and toward theviewer, and IC1=1 represents that the current IC1 is flowing in adirection perpendicular to the plane of the drawing and away from theviewer. Also, IC2=0 represents that the current IC2 is flowing in adirection perpendicular to the plane of the drawing and toward theviewer, and IC2=1 represents that the current IC2 is flowing in adirection perpendicular to the plane of the drawing and away from theviewer. The directions of the magnetic fields generated around the inputlines 167 and 169 are shown by the arcuate arrows.

When the currents IC1 and IC2 are flowing in the same direction as shownin FIG. 16A and FIG. 16D, since the magnetic fields generated around theinput lines 167 and 169 are cancelled by each other in an area in thevicinity of the TMR element 151, the magnetizing direction of theferromagnetic layer 163 is not changed. That is, the content stored inthe ferromagnetic layer 163 is not changed from that before a writingprocess.

On the other hand, when the current IC1 and IC2 are flowing in theopposite directions as shown in FIG. 16B and FIG. 16C, since themagnetic fields generated around the input lines 167 and 169 areenhanced by each other in an area in the vicinity of the TMR element151, the magnetizing direction of the ferromagnetic layer 163 is changedto the rightward direction (first magnetizing direction) or the leftwarddirection (second magnetizing direction) in the drawings. That is, thecontent stored in the ferromagnetic layer 163 is renewed depending onthe directions of the currents IC1 and IC2 by a writing process.

As described above, by controlling the currents IC1 and IC2, data can bewritten into the TMR element 151.

FIG. 17A and FIG. 17B are views used to explain a method for controllingthe transistor MP based on data written into the TMR element 151, thatis, a method for performing a reading process. The gate terminal of thetransistor MP is connected to the terminal 161 a of the TMR element 151via the input line 167. The terminal 163 a of the TMR element 151 isconnected to a power source 153 via the input line 169.

The electrical resistance of the TMR element 151 is decreased when themagnetizing directions of the ferromagnetic layers 161 and 163 are thesame and increases when the magnetizing directions of the ferromagneticlayers 161 and 163 are different by a tunnel magnetoresistive effect.Thus, as shown in FIG. 17A and FIG. 17B, when the voltage of the powersource 153 is constant (the source voltage Vdd, for example), thecurrent which flows through the TMR element 151 when the magnetizingdirection of the ferromagnetic layer 163 is rightward is greater thanthe current which flows when the magnetizing direction of theferromagnetic layer 163 is leftward. Using this, the transistor MP iscontrolled based on data written into the TMR element 151.

When the state in which the magnetizing direction of the ferromagneticlayer 163 before a writing process is rightward and the state in whichthe magnetizing direction of the ferromagnetic layer 163 before awriting process is leftward are associated with state data (that is,non-volatile states corresponding to a specified logical operator) s=1and s=0, respectively, when the directions IC1=0 and IC1=1 of thecurrent IC1 which is passed through the input line 167 in a writingprocess are associated with first operation target data y1=0 and y1=1,respectively, when the directions IC2=0 and IC2=1 of the current IC2which is passed through the input line 169 in a writing process areassociated with second operation target data y2=0 and y2=1,respectively, and when the case in which the transistor MP becomes onwhen the source potential Vdd is given to the input line 169 in areading process and the case in which the transistor MP becomes off whenthe source potential Vdd is given to the input line 169 in a readingprocess are associated with operation result data z=0 and z=1,respectively, the logical operation circuit of this embodiment satisfiesthe following relation as in the case with the before-mentioned logicaloperation circuit using a ferroelectric capacitor as a non-volatilememory element:

-   -   z=/s AND y1 NAND /y2 OR s AND (y1 NOR /y2).

A logical operation circuit according to this invention comprises: afirst ferroelectric capacitor, first and second signal lines and anoperation result output section. The first ferroelectric capacitor canretain a polarization state corresponding to a specified logicaloperator, and has first and second terminals. The first and secondsignal lines can provide first and second operation target data to thefirst and second terminals, respectively, of the ferroelectric capacitorretaining the polarization state corresponding to the logical operator,and are connected to the first and second terminals, respectively. Theoperation result output section can output the result of a logicaloperation performed on the first and second operation target dataaccording to the logical operator based on a polarization state of theferroelectric capacitor generated by providing the two operation targetdata to the ferroelectric capacitor, and is connected to the firstsignal line.

A logical operation method according to this invention comprises thesteps of: causing a ferroelectric capacitor having first and secondterminals to retain a polarization state corresponding to a specifiedlogical operator; providing first and second operation target data tothe first and second terminals, respectively, of the ferroelectriccapacitor retaining the polarization state corresponding to the logicaloperator; and obtaining the result of a logical operation performed onthe first and second operation target data according to the logicaloperator based on the polarization state of the ferroelectric capacitorgenerated by providing the two operation target data to theferroelectric capacitor.

According to the above logical operation circuit or the logicaloperation method, when a polarization state of the first ferroelectriccapacitor and the result of a logical operation are associated with eachother, it is possible to obtain, based on a new polarization state ofthe first ferroelectric capacitor generated by providing the first andsecond operation target data to the first ferroelectric capacitorretaining a polarization state corresponding to the specified logicaloperator, the result of the logical operation performed on the first andsecond operation target data according to the logical operator. That is,a logical operation can be performed on data using a ferroelectriccapacitor.

In the logical operation circuit according to this invention, the firstand second signal lines are connected to one of first and secondreference potentials and the other of the first and second referencepotentials, respectively, to generate the polarization statecorresponding to the logical operator in the first ferroelectriccapacitor before the first and second operation target data areprovided.

Thus, a desired logical operator can be stored in the ferroelectriccapacitor via the first and second signal lines. Therefore, the logicaloperator, as well as the first and second operation target data, can berewritten as needed. That is, a desired logical operation can beperformed on any two data.

In the logical operation circuit according to this invention, theoperation result output section has a load element having a thirdterminal connected to the first signal line and a fourth terminalconnected to the first reference potential, and, when outputting theresult of the logical operation, connects the first signal line to thefirst reference potential and releases the connection, then connects thesecond signal line to the second reference potential different from thefirst reference potential, and outputs the logical operation resultbased on a potential generated in the first signal line when the secondsignal line is connected to the second reference potential.

Thus, by properly setting the characteristics of the first ferroelectriccapacitor and the load element, the result of the logical operation canbe reliably obtained based on a divided voltage generated in the loadelement.

In the logical operation circuit according to this invention, theoperation result output section has an output transistor which has acontrol terminal connected to the first signal line and an outputterminal for outputting an output signal corresponding to a controlsignal inputted into the control terminal. The output transistor becomesoff when a potential on the first reference potential side from itsthreshold voltage is given as the control signal and becomes on when apotential on the second reference potential side from its thresholdvoltage is given as the control signal. The result of the logicaloperation is obtained as an output signal from the output transistor.

The output transistor becomes off when the potential generated in thefirst signal line based on a new polarization state of the firstferroelectric capacitor generated by providing the first and secondoperation target data to the first ferroelectric capacitor retaining apolarization state corresponding to the logical operator is on the firstreference potential side from the threshold voltage and becomes on whenthe potential is on the second reference potential side from thethreshold voltage. Thus, by properly setting the threshold voltage ofthe output transistor, the result of the logical operation can beobtained as an output signal from the output transistor.

A logical operation circuit according to this invention comprises: afirst ferroelectric capacitor having first and second terminals; firstand second signal lines connected to the first and second terminals,respectively; a second ferroelectric capacitor having a third terminalconnected to the first signal line and a fourth terminal connected to afirst reference potential; and an output transistor. The outputtransistor has a control terminal connected to the first signal line andan output terminal for outputting an output signal corresponding to acontrol signal inputted into the control terminal, and becomes off whena potential on the first reference potential side from its thresholdvoltage is given as the control signal and becomes on when a potentialon a second reference potential side from its threshold voltage is givenas the control signal. In the logical operation circuit, the followingoperation is performed: The first and second signal lines are connectedto one of the first and second reference potentials and the other of thefirst and second reference potentials, respectively, to generate apolarization state corresponding to a specified logical operator in thefirst ferroelectric capacitor. Then, first and second operation targetdata are provided to the first and second signal lines, respectively, toshift the polarization state of the first ferroelectric capacitor to onecorresponding to the combination of the logical operator and the firstand second operation target data. The first and second signal lines areboth connected to the first reference potential to precharge the firstsignal line to the first reference potential without changing theresidual polarization state of the first ferroelectric capacitor. Afterthat, the application of voltage to the first signal line is stopped andthe second signal line is connected to the second reference potential.Then, an output signal which is generated at the output terminal of theoutput transistor in response to a potential generated in the firstsignal line when the second signal line is connected to the secondreference potential can be obtained as the result of a logical operationperformed on the first and second operation target data according to thelogical operator.

Thus, by properly setting the threshold voltage of the outputtransistor, the result of the logical operation can be obtained as anoutput signal from the output transistor. That is, a logical operationcan be performed on data using a ferroelectric capacitor.

In the logical operation circuit according to this invention, theresidual polarization state of the first ferroelectric capacitordetermined by the combination of the logical operator and the first andsecond operation target data is either a first residual polarizationstate or a second residual polarization state having a polarizationdirection opposite that of the first residual polarization state. Also,the output transistor has a threshold voltage between two potentialswhich can be generated in the first signal line during a logicaloperation in response to the first and second residual polarizationstates, respectively, of the first ferroelectric capacitor.

Thus, the result of the logical operation retained as a first or secondresidual polarization state of the first ferroelectric capacitor can beeasily represented directly in the form of the on or off state of theoutput transistor.

In the logical operation circuit according to this invention, the loadelement is a second ferroelectric capacitor. Thus, since the firstferroelectric capacitor and the load element can be produced by the sameprocess, errors deriving from the differences in the productionprocesses can be reduced. It is, therefore, possible to obtain a logicaloperation circuit with high reliability.

A logical operation circuit according to this invention comprises: anon-volatile memory element which can retain a non-volatile statecorresponding to a specified logical operator and which has first andsecond terminals; and an operation result output section which, based ona state of the non-volatile memory element generated by providing firstand second operation target binary data y1 and y2 to the first andsecond terminals, respectively, of the non-volatile memory element,outputs the result of a logical operation performed on the first andsecond operation target data y1 and y2 according to the logical operatoras operation result binary data “z”. When the non-volatile statecorresponding to the specified logical operator is represented by statebinary data “s”, the operation result data “z” substantially satisfiesthe following relation:

-   -   z=/s AND y1 NAND /y2 OR s AND (y1 NOR /y2).

Thus, when a non-volatile state of the non-volatile memory element andoperation result data “z” are associated with each other, it is possibleto obtain, based on a new non-volatile state of the non-volatile elementwhich can be generated by providing the first and second operationtarget data y1 and y2 to the non-volatile memory element retaining anon-volatile state “s” corresponding to a specified logical operator,the result “z” of a logical operation performed on the first and secondoperation target data y1 and y2 according to the logical operator. Thatis, a logical operation can be performed on data using a non-volatilememory element. Also, by controlling the non-volatile state “s” of thenon-volatile memory element before the provision of the first and secondoperation target data y1 and y2, a desired logical operation can beperformed.

In the logical operation circuit according to this invention, thenon-volatile memory element includes a ferroelectric capacitor and thenon-volatile state is a residual polarization state of the ferroelectriccapacitor. Thus, since a ferroelectric capacitor is used as thenon-volatile memory element, a writing process can be performed on a lowvoltage at a high speed.

A logical operation circuit according to this invention comprises: anon-volatile memory element for retaining a non-volatile statecorresponding to a specified logical operator; and an operation resultoutput section which, based on a state of the non-volatile memoryelement generated by providing first and second operation target data tothe non-volatile memory element, outputs the result of a logicaloperation performed on the first and second operation target dataaccording to the logical operator, and which is connected to a firstterminal of the non-volatile memory element.

Thus, when a non-volatile state of the non-volatile memory element andthe result of a logical operation are associated with each other, it ispossible to obtain, based on a new non-volatile state of thenon-volatile element which can be generated by providing the first andsecond operation target data to the non-volatile memory elementretaining a non-volatile state corresponding to a specified logicaloperator, the result of a logical operation performed on the first andsecond operation target data according to the logical operator. That is,a logical operation can be performed on data using a non-volatile memoryelement.

A logical operation device according to this invention comprises aplurality of logical operation circuits of any of the above types whichare arranged in series and/or parallel to perform a desired logicaloperation.

Since a multiplicity of the logical operation circuits, each of whichcan serve as a logical operation section and a storage section, arecombined to perform a desired logical operation, it is possible toobtain a logical operation device which has a smaller circuit area,including the area for wiring, than a conventional logical operationdevice having a separate storage section does. Thus, the degree ofintegration in the device can be highly increased, and the powerconsumption of the device can be reduced. Also, since the storage isnon-volatile, no power is required to retain the storage. Thus, powerconsumption during operation can be reduced, and little power isconsumed during standby. Also, there is no need for a backup powersource for power shutdown. In addition, when an element including aferroelectric capacitor is used as a non-volatile memory element, awriting process can be performed at a high speed.

A logical operation device according to this invention comprises aplurality of logical operation circuits of any of the above types whichare arranged in series and/or parallel to perform an addition of atleast two binary numbers.

Since an adder is constituted of a multiplicity of the logical operationcircuits, each of which can serve as a logical operation section and astorage section, the circuit area of the adder, including the area forwiring, can be much smaller than that of a conventional adder. Thus, thedegree of integration in the device can be highly increased, and thepower consumption of the device can be reduced. Also, since the storageis non-volatile, no power is required to retain the storage. Thus, powerconsumption during the addition operation can be reduced, and littlepower is consumed during standby. Also, there is no need for a backuppower source for power shutdown. In addition, when an element includinga ferroelectric capacitor is used as a non-volatile memory element, awriting process can be performed at a high speed.

In the logical operation device according to this invention, the atleast two binary numbers are three binary numbers: an augend, an adderand a carry from a lower bit. The logical operation device furthercomprises: an addition result calculation section for calculating theresult of an addition of the three binary numbers; and a carrycalculation section for calculating the carry of the addition of thethree binary numbers. The addition result calculation section calculatesa binary number corresponding to the exclusive OR of binary numberscorresponding to two of the three binary numbers as a first additionresult using a pair of the logical operation circuits connected inparallel, calculates a binary number corresponding to the exclusive ORof the first addition result and a binary number corresponding to theother of the three binary numbers as a second addition result usinganother pair of the logical operation circuits connected in parallel,and provides the second addition result as its output. The carrycalculation section calculates the carry of the addition of the threebinary numbers based on the three binary numbers using a plurality ofthe logical operation circuits, and provides the calculated carry as itsoutput.

Thus, a full adder can be constituted of two pair of logical operationcircuits for calculating and storing the result of an addition and aplurality of logical operation circuits for calculating and storing acarry. It is, therefore, possible to realize a highly-integrated,low-power consumption full adder with ease.

A logical operation device according to this invention comprises aplurality of logical operation circuits of any of the above types whichare arranged in series and/or parallel to perform a logical operation,in which the logical operation is divided into a plurality of stages,which are executed in sequence.

Since each of the stages is constituted of a multiplicity of the logicaloperation circuits, each of which serves as a logical operation sectionand a storage section, it is possible to obtain a pipelined logicaloperation device which has a smaller circuit area, including the areafor wiring, than a conventional pipelined logical operation device does.Thus, the degree of integration in the device can be highly increased,and the power consumption of the device can be reduced. Also, since thestorage is non-volatile, no power is required to retain the storage.Thus, power consumption during operation can be reduced, and littlepower is consumed during standby. Also, there is no need for a backuppower source for power shutdown. In addition, when an element includinga ferroelectric capacitor is used as a non-volatile memory element, awriting process can be performed at a high speed.

In the logical operation device according to this invention, the logicaloperation includes an addition of three binary numbers: an augend, anadder and a carry from a lower bit. The logical operation device furthercomprises: a first addition stage operation section for performing afirst addition stage operation including a process of calculating andstoring a binary number corresponding to the exclusive OR of binarynumbers corresponding to two of the three binary numbers as a firstaddition result using a pair of the logical operation circuits connectedin parallel; and a second addition stage operation section forperforming, subsequently to the first addition stage operation, a secondaddition stage operation including a process of calculating and storinga binary number corresponding to the exclusive OR of the first additionresult and a binary number corresponding to the other of the threebinary numbers as a second addition result and outputting the secondaddition result as the result of the addition of the logical operationdevice using another pair of the logical operation circuits connected inparallel, and a process of outputting the carry of the addition of thethree binary numbers based on the three binary numbers using a pluralityof the logical operation circuits.

Thus, a pipelined full adder can be constituted when two pairs oflogical operation circuits for calculating an addition result and aplurality of logical operation circuits for calculating a carry whichare disposed separately in two stage operation sections. It is,therefore, possible to constitute a highly-integrated, low-powerconsumption, pipelined full adder with ease.

A logical operation device according to this invention is a logicaloperation circuit for dividing a multiplication of two binary numbersinto a plurality of levels and performing them in sequence, andcomprises: a partial product generation section for generating a partialproduct of a multiplicand and a multiplier; and an addition sectionincluding a plurality of logical operation devices as element operationdevices which are arranged in a plurality of stages corresponding to theplurality of levels and which receive the partial product and/or theaddition result in the previous stage and perform additions in sequenceto obtain an operation result.

Thus, a pipelined multiplier can be constituted when the above pipelinedfull adders as element operation devices are arranged in a plurality ofstages corresponding to the levels of the multiplication. It is,therefore, possible to constitute a highly-integrated, low-powerconsumption, pipelined multiplier with ease.

In the logical operation device according to this invention, the numberof the levels is the same as the bit number of the multiplier or more,the partial product generation section is constituted of element partialproduct generation sections located in level operation sections each forperforming an operation of each level, and the addition section isconstituted of the element operation devices located in level operationsections for performing the operations of at least the second level andlater. Each of the level operation sections for performing theoperations of at least the second level and later has a first stageoperation section for performing a first stage operation including aprocess of storing one bit of bits constituting the multiplicand whichis the target of the current operation as an operation targetmultiplicand bit; a second stage operation section for performing,subsequently to the first stage operation, a second stage operationincluding a process of calculating and storing the AND of the operationtarget multiplicand bit and a bit corresponding to the relevant level ofthe bits constituting the multiplier as an element partial product ofthe operation target multiplicand bit in the relevant level using theelement partial product generation section, and third and fourth stageoperation sections for performing, subsequently to the second stageoperation, third and fourth stage operations respectively, including aprocess of calculating the sum of three binary numbers: an elementpartial product in the relevant level, a partial product in the previouslevel and a carry of the bit before the operation target multiplicandbit in the relevant level and storing it as a partial product of theoperation target multiplicand bit in the relevant level, and storing thecarry generated by the addition as a carry of the operation targetmultiplicand bit in the relevant level.

Thus, a series-parallel pipelined multiplier can be constituted bygiving a corresponding bit value to each of the level operation sectionscorresponding in number to the bit number of the multiplier, giving thebit values of the multiplicand to the first level operation section insequence, and giving the bit values of the multiplicand to each of thelevel operations sections of intermediate levels from a previous leveloperation section in sequence with a specified delay. It is, therefore,possible to constitute a highly-integrated, low-power consumption,series-parallel pipelined multiplier with ease.

While this invention has been described in its preferred embodiments, itis understood that the terminology employed herein is for the purpose ofdescription and not of limitation and that changes and variations may bemade without departing from the spirit and scope of the appended claims.

1. A logical operation circuit comprising: a first ferroelectriccapacitor which can retain a polarization state corresponding to aspecified logical operator and which has first and second terminals;first and second signal lines which can provide first and secondoperation target data to the first and second terminals, respectively,of the ferroelectric capacitor retaining the polarization statecorresponding to the logical operator and which are connected to thefirst and second terminals, respectively; and an operation result outputsection which outputs the result of a logical operation performed on thefirst and second operation target data according to the logicaloperator, based on a polarization state of the ferroelectric capacitorgenerated by providing the two operation target data to theferroelectric capacitor, and which is connected to the first signalline.
 2. The logical operation circuit as set forth in claim 1, whereinthe first and second signal lines are connected to one of first andsecond reference potentials and the other of the first and secondreference potentials, respectively, to generate the polarization statecorresponding to the logical operator in the first ferroelectriccapacitor before the first and second operation target data areprovided.
 3. The logical operation circuit as set forth in claim 1 or 2,wherein the operation result output section has a load element having athird terminal connected to the first signal line and a fourth terminalconnected to the first reference potential, and, when outputting theresult of the logical operation, connects the first signal line to thefirst reference potential and releases the connection, then connects thesecond signal line to the second reference potential, and outputs thelogical operation result based on a potential generated in the firstsignal line when the second signal line is connected to the secondreference potential.
 4. The logical operation circuit as set forth inclaim 3, wherein the operation result output section has an outputtransistor which has a control terminal connected to the first signalline and an output terminal for outputting an output signalcorresponding to a control signal inputted into the control terminal,and which becomes off when a potential on the first reference potentialside from its threshold voltage is given as the control signal andbecomes on when a potential on the second reference potential side fromits threshold voltage is given as the control signal, and wherein theresult of the logical operation is obtained as an output signal from theoutput transistor.
 5. A logical operation circuit comprising: a firstferroelectric capacitor having first and second terminals; first andsecond signal lines connected to the first and second terminals,respectively; a second ferroelectric capacitor having a third terminalconnected to the first signal line and a fourth terminal connected to afirst reference potential; and an output transistor which has a controlterminal connected to the first signal line and an output terminal foroutputting an output signal corresponding to a control signal inputtedinto the control terminal, and which becomes off when a potential on thefirst reference potential side from its threshold voltage is given asthe control signal and becomes on when a potential on a second referencepotential side from its threshold voltage is given as the controlsignal, wherein the first and second signal lines are connected to oneof the first and second reference potentials and the other of the firstand second reference potentials, respectively, to generate apolarization state corresponding to a specified logical operator in thefirst ferroelectric capacitor, first and second operation target dataare provided to the first and second signal lines, respectively, toshift the polarization state of the first ferroelectric capacitor to onecorresponding to the combination of the logical operator and the firstand second operation target data, the first and second signal lines areboth connected to the first reference potential to precharge the firstsignal line to the first reference potential without changing theresidual polarization state of the first ferroelectric capacitor, andthe application of voltage to the first signal line is stopped and thesecond signal line is connected to the second reference potential, andan output signal which is generated at the output terminal of the outputtransistor in response to a potential generated in the first signal linewhen the second signal line is connected to the second referencepotential is obtained as the result of a logical operation performed onthe first and second operation target data according to the logicaloperator.
 6. The logical operation circuit as set forth in claim 4 5,wherein the residual polarization state of the first ferroelectriccapacitor determined by the combination of the logical operator and thefirst and second operation target data is either a first residualpolarization state or a second residual polarization state having apolarization direction opposite that of the first residual polarizationstate, and wherein the output transistor has a threshold voltage betweentwo potentials which can be generated in the first signal line during alogical operation in response to the first and second residualpolarization states, respectively, of the first ferroelectric capacitor.7. The logical operation circuit as set forth in claim 3, wherein theload element is a second ferroelectric capacitor.
 8. A logical operationcircuit comprising: a non-volatile memory element which can retain anon-volatile state corresponding to a specified logical operator andwhich has first and second terminals; and an operation result outputsection which, based on a state of the non-volatile memory elementgenerated by providing first and second operation target binary data y1and y2 to the first and second terminals, respectively, of thenon-volatile memory element, outputs the result of a logical operationperformed on the first and second operation target data y1 and y2according to the logical operator as operation result binary data “z”,wherein, when the non-volatile state corresponding to the specifiedlogical operator is represented by state binary data “s”, the operationresult data “z” substantially satisfies the following relation: z=/s ANDy1 NAND /y2 OR s AND (y1 NOR /y2).
 9. The logical operation circuit asset forth in claim 8, wherein the non-volatile memory element includes aferroelectric capacitor and the non-volatile state is a residualpolarization state of the ferroelectric capacitor.
 10. A logicaloperation circuit comprising: a non-volatile memory element forretaining a non-volatile state corresponding to a specified logicaloperator; and an operation result output section which, based on a stateof the non-volatile memory element generated by providing first andsecond operation target data to the non-volatile memory element, outputsthe result of a logical operation performed on the first and secondoperation target data according to the logical operator, and which isconnected to a first terminal of the non-volatile memory element.
 11. Alogical operation device comprising a plurality of logical operationcircuits according to claim 10, which are arranged in series and/orparallel to perform a desired logical operation.
 12. A logical operationdevice comprising a plurality of logical operation circuits according toclaim 10, which are arranged in series and/or parallel to perform anaddition of at least two binary numbers.
 13. The logical operationdevice as set forth in claim 12, wherein the at least two binary numbersare three binary numbers: an augend, an adder and a carry from a lowerbit, the logical operation device further comprising an addition resultcalculation section for calculating the result of an addition of thethree binary numbers and a carry calculation section for calculating thecarry of the addition of the three binary numbers, wherein the additionresult calculation section calculates a binary number corresponding tothe exclusive OR of binary numbers corresponding to two of the threebinary numbers as a first addition result using a pair of the logicaloperation circuits connected in parallel, calculates a binary numbercorresponding to the exclusive OR of the first addition result and abinary number corresponding to the other of the three binary numbers asa second addition result using another pair of the logical operationcircuits connected in parallel, and provides the second addition resultas its output, and wherein the carry calculation section calculates thecarry of the addition of the three binary numbers based on the threebinary numbers using a plurality of the logical operation circuits, andprovides the calculated carry as its output.
 14. A logical operationdevice comprising a plurality of logical operation circuits according toclaim 10, which are arranged in series and/or parallel to perform alogical operation, wherein the logical operation is divided into aplurality of stages, which are executed in sequence.
 15. The logicaloperation device as set forth in claim 12, Wherein the logical operationincludes an addition of three binary numbers: an augend, an adder and acarry from a lower bit, the logical operation device further comprising:a first addition stage operation section for performing a first additionstage operation including a process of calculating and storing a binarynumber corresponding to the exclusive OR of binary numbers correspondingto two of the three binary numbers as a first addition result using apair of the logical operation circuits connected in parallel; and asecond addition stage operation section for performing, subsequently tothe first addition stage operation, a second addition stage operationincluding a process of calculating and storing a binary numbercorresponding to the exclusive OR of the first addition result and abinary number corresponding to the other of the three binary numbers asa second addition result and outputting the second addition result asthe result of the addition of the logical operation device using anotherpair of the logical operation circuits connected in parallel, and aprocess of outputting the carry of the addition of the three binarynumbers based on the three binary numbers using a plurality of thelogical operation circuits.
 16. A logical operation device for dividinga multiplication of two binary numbers into a plurality of levels andperforming them in sequence, comprising: a partial product generationsection for generating a partial product of a multiplicand and amultiplier; and an addition section including a plurality of logicaloperation devices according to claim 15, as element operation devices,which are arranged in a plurality of stages corresponding to theplurality of levels and which receive the partial product and/or theaddition result in the previous stage and perform additions in sequenceto obtain an operation result.
 17. The logical operation device as setforth in claim 16, wherein the number of the levels is the same as thebit number of the multiplier or more, wherein the partial productgeneration section is constituted of element partial product generationsections located in level operation sections each for performing anoperation of each level, and wherein the addition section is constitutedof the element operation devices located in level operation sections forperforming the operations of at least the second level and later, eachof the level operation sections for performing the operations of atleast the second level and later having: a first stage operation sectionfor performing a first stage operation including a process of storingone bit of bits constituting the multiplicand which is the target of thecurrent operation as an operation target multiplicand bit; a secondstage operation section for performing, subsequently to the first stageoperation, a second stage operation including a process of calculatingand storing the AND of the operation target multiplicand bit and a bitcorresponding to the relevant level of the bits constituting themultiplier as an element partial product of the operation targetmultiplicand bit in the relevant level using the element partial productgeneration section, and third and fourth stage operation sections forperforming, subsequently to the second stage operation, third and fourthstage operations respectively, including a process of calculating thesum of three binary numbers: an element partial product in the relevantlevel, a partial product in the previous level and a carry of the bitbefore the operation target multiplicand bit in the relevant level andstoring it as a partial product of the operation target multiplicand bitin the relevant level, and storing the carry generated by the additionas a carry of the operation target multiplicand bit in the relevantlevel.
 18. A logical operation method comprising the steps of: causing aferroelectric capacitor having first and second terminals to retain apolarization state corresponding to a specified logical operator;providing first and second operation target data to the first and secondterminals respectively, of the ferroelectric capacitor retaining thepolarization state corresponding to the logical operator; and obtainingthe result of a logical operation performed on the first and secondoperation target data according to the logical operator based on thepolarization state of the ferroelectric capacitor generated by providingthe two operation target data to the ferroelectric capacitor.